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V86 mode is entered through IRETD when the VM bit is set in the stacked EFLAGS. The microcode detects this with a conditional jump:
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The 386 microcode sequencer has a one-cycle pipeline delay: when a jump or RNI (run next instruction) is decoded, the micro-instruction immediately after it has already been fetched and will execute before the jump takes effect. This "delay slot" is a basic property of the sequencer, and the microcode is written to fill it with useful work rather than waste a cycle on a bubble. The examples in the PTSAV section above show this: at 582/5AE, the micro-instruction after LCALL executes before the subroutine begins.，这一点在heLLoword翻译官方下载中也有详细论述
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